Adding Custom Instruction to RISCV-LLVM Backend(Full pipeline- End-to-End)

Adding a new custom instruction in RISCV-LLVM Backend(Full pipeline from LLVM IR to RISCV Assembly to Machine Hex Code)

Hacking the internals of LLVM Backend(Tablegen)

Contribution to the following files:

LLVM IR -> asm code -> binary encodings [Internals]

Step 1: LLVM IR → RISCV asm code (llc tool)

Step 2:

MachineInst → MCLayer → MCInst → MCStreamer → MCAsmStreamer → AsmWriter → .s file

                                            → MCObjectStreamer → MC Code Emitter → .o file → elf Writer → sections like .text, .rela.text, .data → linker(ld) → executable