/tags/blog/ Recent content in blog on Hugo -- gohugo.io en-us Mon, 27 Apr 2026 00:00:00 +0000 /posts/bioxcomputing_interview_early_stage_founder/ Mon, 27 Apr 2026 00:00:00 +0000 /posts/bioxcomputing_interview_early_stage_founder/ Deep-Tech discussions with an early stage founder in BioxComputing domain. [Work In Progress] /posts/hello_world_to_bare_bones_binary/ Fri, 17 Apr 2026 00:00:00 +0000 /posts/hello_world_to_bare_bones_binary/ STAGE 1: Preprocessing Command: gcc -E hello.c -o hello.i What happens: #include <stdio.h> gets replaced by the entire contents of stdio.h, thousands of lines of function declarations, type definitions, macros. printf is not defined yet, just declared. The preprocessor doesn’t know what printf does, just that it exists. Output: hello.i, pure C code, no # directives, just expanded text. Roughly 800 lines for this tiny program. // ... thousands of lines from stdio. /posts/syscall_internals/ Fri, 10 Apr 2026 00:00:00 +0000 /posts/syscall_internals/ There’s an interesting history for this post, I gave an interview at IBM for a compiler engineering position. The discussion was so fun and revolved around everything from C to Low level compiler and OS stuff including computer architecture level intricacies. We delved deep into the privilege escalation(user to kernel mode), runtime stack, and eventually syscalls, interrupts/TRAP. Basic question was the difference between an interrupt and a syscall which anyone can answer but it gets interesting when we start looking at the syscall as a main character. /posts/multiple_process_communication_in_os/ Fri, 03 Apr 2026 00:00:00 +0000 /posts/multiple_process_communication_in_os/ Understanding the processes-process communication in depth at OS level This is again coming from one of the interviews discussions at IBM for compiler role. /posts/c_lang_intricacies/ Sat, 28 Mar 2026 00:00:00 +0000 /posts/c_lang_intricacies/ Over the past few years, through my work with Unikraft on unikernels, a compiler research internship at CERN/Berkeley Lab, hardware–software co-design at Vicharak Computers, and systems research for neuromorphic chips at IISc, I’ve been trying to find my place in the low-level world. But I kept running into the same wall: a lack of deep understanding of C’s intricacies the kind that every serious low-level engineer or hacker is expected to master. /posts/reverse_engineering_101/ Sat, 21 Mar 2026 00:00:00 +0000 /posts/reverse_engineering_101/ When nothing goes right, you open your laptop and you end-up doing things that you would anyways do whatever the fk is going on in the world, for me it has been the love for understanding my computer. Reverse Engineering grounds me and improves my focus and it wouldn’t be wrong to call it as a “mindset” rather than a “discipline”. /posts/xpus_not_gpus_energy_efficient_future/ Fri, 13 Feb 2026 00:00:00 +0000 /posts/xpus_not_gpus_energy_efficient_future/ My remote interview experience with Co-founder/CEO of Zettascale Computing Corp(YCombinator funded deep-tech startup), this time it was XPUs not GPUs or TPUs. Technical discussions- Architecture-level questions: -> Why are you even doing this? Impact? Real impact not how the next ChatGPT will be much more faster. → Creative models like BNNs or LGNs don’t work well on GPUs. → They quickly get disregarded. What about training BNNs on XPUs? Will we be able to train them on XPUs because on GPUs they are extremely slow? /posts/figuring-out-low-level-stack-for-novel-architectures/ Sun, 04 Jan 2026 00:00:00 +0000 /posts/figuring-out-low-level-stack-for-novel-architectures/ This isn’t just another roadmap but my personal low-level learning path(which will never end I know) that I have been following while figuring out complete end-to-end low-level stack for a novel computing architecture based on memristors in-memory brain-inspired chip. Questions to answer: “How does userspace talk to hardware?” “Where do syscalls actually live?” “How would my neuromorphic accelerator appear to Linux?” “How does the kernel map physical devices to memory?” “How would I add a new instruction or device? /projects/short_primer_on_logic_gate_networks/ Fri, 21 Mar 2025 00:00:00 +0000 /projects/short_primer_on_logic_gate_networks/ A logic gate network is a neural network which consists of logic gates in the form of neurons. A traditional neural network consist of the following component: neurons connections(weights) Every neuron has properties like bias and weights. During a NN training, these weights are learned and updated at every layer during back propagation. In a logic gate network, instead of having a 32 bit floating point weights, we have a network which is weightless. /posts/hacking_llvm_ir/ Mon, 18 Nov 2024 00:00:00 +0000 /posts/hacking_llvm_ir/ Another interview motivation post, this time it was NVIDIA LLVM IR engineering intern position. They wanted me to have contributed to a real open source codebase specifically in LLVM/LLVM IR. So, here I will try to explain some of the interesting hacks about LLVM IR, experiments I did and what I learnt. I have learned this very hard way that it doesn’t matter if you know 100s of topics or concepts or have read dozens of technical blogs. /posts/breaking_down_unikernels/ Tue, 01 Aug 2023 00:00:00 +0000 /posts/breaking_down_unikernels/